RISCV-BOOM
cleanup-docs

Introduction:

  • The Berkeley Out-of-Order Machine (BOOM)
  • The BOOM Pipeline
  • The Chisel Hardware Construction Language
  • The RISC-V ISA
  • Rocket Chip SoC Generator

Core Overview:

  • Instruction Fetch
  • Branch Prediction
  • The Decode Stage
  • The Rename Stage
  • The Reorder Buffer (ROB) and the Dispatch Stage
  • The Issue Unit
  • The Register Files and Bypass Network
  • The Execute Pipeline
  • The Load/Store Unit (LSU)
  • The Memory System

Usage:

  • Parameterization
  • The BOOM Development Ecosystem
  • Debugging
  • Micro-architectural Event Tracking
  • Verification
  • Physical Realization

Other:

  • Future Work
  • Frequently Asked Questions
  • Terminology
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